ICX224AK |
RFQ for ICX224AK Required Field |
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| Product | Manufacturers | Pack | D/C |
| ICX224AK | - | 00+ | DIP20() |
The ICX224AK is a diagonal 8mm (Type 1/2) interline CCD solid-state image sensor with a square pixel array and 2.02M effective pixels. Frame readout allows all pixels' signals to be output independently within approximately 1/7.5 second. Also, the adoption of high frame rate readout mode supports 30 frames per second which is four times the speed in frame readout mode. This chip features an electronic shutter with variable charge-storage time. Adoption of a design specially suited for frame readout ensures a saturation signal level equivalent to when using field readout. Ye, Cy, Mg, G complementary color mosaic filters are used as the color filters, and at the same time high sensitivity and low dark current are achieved through the adoption of Super HAD CCD technology.
This chip is suitable for applications such as electronic still cameras, PC input cameras, etc.
Features |
| • Supports frame readout• High horizontal and vertical resolution• Supports high frame rate readout mode: 30 frames/s• Square pixel• Horizontal drive frequency: 18MHz• No voltage adjustments (reset gate and substrate bias are not adjusted.)• Ye, Cy, Mg, G complementary color mosaic filters on chip• High sensitivity, low smear• Continuous variable-speed shutter• Low dark current, excellent anti-blooming characteristics• 20-pin high-precision plastic package (top/bottom dual surface reference possible) |
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Item |
Ratings | Unit | Remarks | |
| Against SUB |
VDD, VOUT, RG SUB |
40 to +12 | V | |
| V1A, V1B, V3A, Vf3B SUB | 50 to +15 | V | ||
| V2, V4, VL SUB | 50 to +0.3 | V | ||
| H1, H2, GND SUB | 40 to +0.3 | V | ||
| CSUB SUB | 25 to | V | ||
| Against GND | VDD, VOUT, RG, CSUB GND | 0.3 to +22 | V | |
| V1A, V1B, V2, V3A, V3B, V4 GND | 10 to +18 | V | ||
| H1, H2 GND | 10 to +6.5 | V | ||
| Against VL | V1A, V1B, V3A, V3B VL | 0.3 to +28 | V | |
| V2, V4, H1, H2, GND VL | 0.3 to +15 | V | ||
| Between input clock pins |
Voltage difference between vertical clock input pins | to +15 | V | *2 |
| H1 H2 | 16 to +6.5 | V | ||
| H1, H2 V4 | 16 to
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